1. Field of the Invention
The invention pertains to computer memory systems which require refresh at predetermined time intervals in order to provide for data retention. In particular, the invention pertains to the use of CCD memories such as in a LARAM device used in a paging store memory application.
2. Description of the Prior Art
CCD's for computer memory purposes have recently become available. The basic charge coupled memory device is a shift register which is constructed as a line of capacitive storage elements which have the ability to pass stored charges from one storage position to the next under the control of a clock signal. As the storage elements are basically capacitive in nature and subject to leakage, it is necessary that the data in each shift register be recirculated or refreshed within a predetermined time interval less the data stored therein be lost.
More recently, multiple CCD shift registers have become available upon a single semiconductor chip. Various organizations have been proposed but the line addressable random access memory (LARAM) structure has been one of the most promising. One such device is described in U.S. Pat. No. 4,024,512, issued on May 17, 1977, to Amelio et al. Therein, a LARAM device structure is described which includes a number of parallel shift registers each of which is coupled to common output and common input buses. Separate address activation or selection lines are provided for selecting or activating a predetermined one of the shift registers within a single device. To read data into a selected shift register, the corresponding address or selection line is activated and the data read in through an input buffer onto the input bus under control of a clock signal and internal control logic. To read the data out, the corresponding address or select line is again activated and a clock signal applied. The data from the selected shift register is then read out upon the output bus through a charge sense amplifier and finally through an output buffer to an data output line. Similarly, to refresh a particular shift register, the corresponding address or select line is activated, the clocking signal applied and the data read out upon the output bus through the charge sense amplifier and then through a regeneration loop back through the control logic and input buffer onto the input bus and back into the same shift register. Because only a single charge sense amplifier is provided for each loop of shift registers, each shift register must be refreshed separately from all the rest and at a different time interval. Also, it is not possible to read data out from one shift register while another shift register in the same LARAM chip is being refreshed.
In medium- and large-scale computer systems, charge coupled device memories have been proposed in a number of configurations for filling a gap between low-speed, low-cost disc memories and high-speed, high-cost random access memories. However, CCD memories have not heretobefore fulfilled their entire potential because of the refresh problem. That is, a significant amount of time must be taken to refresh the devices which adds to the total time required to read data from memory employing these devices.
One memory system in which CCD's can be used to advantage is termed the paging store-type memory. In the organization of this memory, a number of parallel-operated memory storage units are provided, all of which connect to a controller through common data, address and control buses. Each memory storage unit, in turn, includes plural memory array units each of which may store a single block or more of data. For the entire set of memory array units within a single memory storage unit, there is provided a single interface logic circuit including an array timing circuit and also a refresh control circuit. Data is always read out from the memory storage units one block at a time. A data block of 4,096 (4 K) bytes of 9 bits each is typical.
Within each memory storage unit, the interface logic circuit, array timing and refresh control circuits determine how data is stored among the various memory array units and control its readout as well as controlling the refresh operation of the memory array units, independent of the read-in and readout of data from the controller. Each memory array unit may include a plurality of shift register elements each of which contains a part of the data. A block of data may begin in any location in one memory array unit and continue on through one or more further memory array units.